Thompson, Ian Vernon; (2003) Strategies for the analysis and design of a low noise, frequency agile synthesiser. Doctoral thesis (Ph.D.), University College London (United Kingdom).

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Abstract

Frequency synthesisers have become the heart of many modem communications systems as they offer a repeatable means of producing a phase coherent signal source of almost arbitrary frequency and precision. In effect, they can be considered as very high-Q tracking filters capable of being digitally programmed to any integer or non-integer multiple of a reference frequency, with a limited amount of extraneous noise. Their relative simplicity and extraordinary benefit to communications systems has led to their success. This thesis explores new strategies aimed at advancing our understanding of the noise and agility performance limits of modem phase locked loop frequency synthesisers and, in tum, allowing their better optimisation. A principal aim of this work is the development of a set of comprehensive models with which to analyse the noise performance of the common synthesiser elements and the system as a whole. A complete rigorous mathematical noise model of a sampled closed-loop phase locked loop synthesiser is developed and compared with measured results from a working prototype synthesiser. To complement this work, a detailed study of the mathematics of loop filter design is offered which does not compromise the loop bandwidth. Further work is presented to determine the fundamental noise limitations in such systems and to optimise the design rationale of synthesisers taking into account sampling effects, which are highly significant in high performance applications. Finally, a novel architecture offering the potential for low noise agile frequency synthesis, "the hybrid PLL/DDS synthesiser", is proposed and assessed both theoretically and experimentally.

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