Padovani, A; Torraca, PL; Larcher, L; Strand, J; Shluger, A; (2023) Modeling Degradation and Breakdown in SiO2 and High-k Gate Dielectrics. In: Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2023. (pp. pp. 93-96). Institute of Electrical and Electronics Engineers (IEEE)

Preview

Text SISPAD_degradation_breakdown_SiO2_high-k_diel_accepted.pdf - Accepted Version Download (753kB) | Preview

Abstract

We present a multiscale device simulation framework for modeling degradation and breakdown (BD) of gate dielectric stacks. It relies on an accurate, material-dependent description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, atomic species generation), and self-consistently models all degradation phases within the same physics-based description: stress-induced leakage current (SILC), soft (SBD), progressive (PBD) and hard breakdown (HBD). This methodology is applied to understand several key aspects related to the reliability of SiO2 and high-k (HK) gate dielectrics: i) characterization and role of defects responsible for the charge transport in fresh and stressed devices (SILC); ii) the differences observed in the SILC behavior of nMOS and pMOS transistors; iii) the degradation of bilayer SiOx/HfO2 stacks; and iv) the voltage dependence of the time-dependent dielectric breakdown (TDDB) distribution.

Download activity - last month

Export as JSONCSVXML

Download activity - last 12 months

Export as JSONCSVXML

Downloads by country - last 12 months

Export as CSVXMLJSON

Archive Staff Only

View Item